Issues with frame data and logic

Today I bring kind of a more complex issue to the table.

Basically, I was trying to build a state-based machine (Basically a machine that uses a binary signal to determine on which state it's on, and what state it should procceed to and what output to give depending on the input) but I ran into an issue. I used a counter set to one which resets to 0 after filling up to limit the signal to 1 frame, so that that upon receiving an input, the instruction would only execute once. However, this is not the case, there seems to be some kind of discrepancy between counters/timers filling up and logic gates. To those who have worked with binary systems, could you give me some intel on your set up? Would it help if I built memory manually instead of using counters? I also tried limiting the input to one frame by mimicking a CLK peak reader gate, but it didn't work (If connect a signal and its NOT form to an AND gate, in theory the AND gate should activate for the littlest time, however this is not the case in LBP)

I already built a more simple way to accomplish what I was trying to do, but I'm afraid this issue may come again in the future. Thanks!

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Originally Posted by iluminacos

Today I bring kind of a more complex issue to the table.

Basically, I was trying to build a state-based machine (Basically a machine that uses a binary signal to determine on which state it's on, and what state it should procceed to and what output to give depending on the input) but I ran into an issue. I used a counter set to one which resets to 0 after filling up to limit the signal to 1 frame, so that that upon receiving an input, the instruction would only execute once. However, this is not the case, there seems to be some kind of discrepancy between counters/timers filling up and logic gates. To those who have worked with binary systems, could you give me some intel on your set up? Would it help if I built memory manually instead of using counters? I also tried limiting the input to one frame by mimicking a CLK peak reader gate, but it didn't work (If connect a signal and its NOT form to an AND gate, in theory the AND gate should activate for the littlest time, however this is not the case in LBP)

I already built a more simple way to accomplish what I was trying to do, but I'm afraid this issue may come again in the future. Thanks!

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easiest way to check is to wire it to a timer set to 0.1, if the signal is active for the shortest time possible in lbp (a single frame) then the timer will only move 1/3 of the way.

the "one-shot" counter you described will output for a single frame no matter the length of the input, it is a commonly used method so i'm not sure why it's not working for you, make sure you aren't using a timer by mistake (it happens, trust me)

the AND gate setup wouldn't work because lbp calculates logic in 33ms frames or "updates", both signals would change within the same frame therefore the AND gate would never receive both signals at the same time.